This application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2009-138083 filed in Japan on Jun. 9, 2009, the entire contents of which are hereby incorporated by reference.
The present invention relates to a field-effect transistor provided with an insulating layer for suppressing current collapse.
Compound semiconductor devices that use compound semiconductors have been proposed. Compound semiconductors are being increasingly employed in the fields of high power and high frequency devices, given that they are physically superior in terms of electron saturation velocity, withstand voltage, thermal conductivity, and the like.
FIG. 4 is a cross-sectional view showing a cross-section of a field-effect transistor according to a Conventional Example 1. Note that hatching of the cross-section has been omitted with consideration for easy viewing of the figure (this similarly applies to figures below).
A field-effect transistor 101 according to Conventional Example 1 is an example of a basic HFET (Heterostructure Field-Effect Transistor) structure using heterojunctions.
The field-effect transistor 101 is provided with a channel layer 111 and a carrier supply layer 112 that are sequentially laminated on a semiconductor substrate 110. Also, a source electrode 121 and a drain electrode 122 are formed as electrodes on the carrier supply layer 112, and a gate electrode 123 is formed between the source electrode 121 and the drain electrode 122. As for the material for the channel layer 111, undoped GaN is used, for example, and as for the carrier supply layer 112, n-type AlGaN is used, for example.
Electrons that become donors by being generated in the carrier supply layer 112 collect in the channel layer 111, and form a channel composed of two-dimensional electron gas called a two-dimensional electron gas layer 115, in a region on the channel layer 111 side near an interface BD between the channel layer 111 and the carrier supply layer 112. The density of the two-dimensional electron gas can be controlled by changing the thickness of a depletion layer formed directly below the gate by a field effect that occurs when a voltage is applied to the gate electrode 123. That is, the current between the source and the drain of the field-effect transistor 101 can be controlled.
FIG. 5 is a cross-sectional view showing a cross-section of a field-effect transistor according to a Conventional Example 2.
In recent years, various improvements to field-effect transistors have been proposed, with the field-effect transistor 102 according to Conventional Example 2 having been proposed, for example. Note that because the basic configuration is similar to the field-effect transistor 101 of Conventional Example 1, only items that differ will be principally described, with the aid of reference numerals.
The field-effect transistor 102 according to Conventional Example 2 is provided with a first insulating layer 131 on the surface of the carrier supply layer 112, in order to suppress current collapse. Note that current collapse is where the current between source and drain decreases when the field-effect transistor 102 is operated at high voltage.
The first insulating layer 131 is formed in order to decrease the occurrence of surface states in the carrier supply layer 112, thought to be the cause of current collapse. SiN is used, for example, as the material of the first insulating layer 131 (e.g., see JP 2007-73555A (Patent Document 1)).
The field-effect transistor 102 is able to suppress current collapse because of being provided with the first insulating layer 131 for suppressing the occurrence of surface states in the carrier supply layer 112. However, on the other hand, there is a problem in that an interface BD between the first insulating layer 131 and the carrier supply layer 112 tends to form a current leakage path.
Consequently, while the field-effect transistor 102 according to Conventional Example 2 is able to suppress current collapse, gate leakage current increases, making it difficult to secure sufficient withstand voltage.
As means for solving such problems, it has been proposed, for example, to form an opening in a portion of the first insulating layer 131 between the gate electrode 123 and the drain electrode 122 (e.g., see JP 2008-219054A (Patent Document 2)). That is, the field-effect transistor according to Patent Document 2 decreases the gate leakage current flowing to the interface between the first insulating layer and the carrier supply layer, using an opening formed between the gate electrode and the drain electrode.
However, there is a problem in that because the field-effect transistor according to Patent Document 2 is provided with the opening in the first insulating layer, surface states occur in the opening, leading to a decrease in current flowing between source and drain, in other words, current collapse, caused by the surface states in the opening. Moreover, while the field-effect transistor of Patent Document 2 is provided with a second insulation film formed in the opening, the occurrence of surface states cannot be prevented. That is, there is a problem in that current collapse occurs in the case where an opening is formed in the first insulating layer with the aim of decreasing gate leakage current.
The present invention has been made in consideration of such circumstances. That is, an object of the present invention is, with regard to a field-effect transistor in which an opening is formed in a first insulating layer, to provide a field-effect transistor capable of insulating an interface between the first insulating layer and a carrier supply layer from a drain electrode, and suppressing current collapse and gate leakage current, by forming the opening between an edge of the first insulating layer and the drain electrode.